With the development of semiconductor device manufacturing technology, integrated circuit with higher performance and more functionality requires higher device density and further decrease in the size and space of or between the components and units. Therefore, process control is highly required in semiconductor device manufacturing process.
The operation speed of semiconductor devices can be promoted by scaling down and the channel length of the MOS transistor is also continuously scaled down. However, as the channel length of the MOS transistor becomes very short, the so-called short channel effect (SCE) and the drain-induced barrier lowering (DIBL) set a serious obstacle to the miniaturization of semiconductor devices.
Because device performance may decrease due to SCE and may not work properly, it is an important objective in semiconductor device manufacturing research to reduce the SCE. The internal mechanical stress in semiconductor device is widely used in adjusting device performance and the SCE can be effectively reduced by applying stress to the channel.
The commonly used method for increasing stress is to operate in the S/D region to form tensile or compressive stress in the channel. For example, in common silicon technology, the transistor channel is aligned along the silicon {110} orientation. In this arrangement, when compressive stress along the channel direction and/or tensile stress perpendicular to the channel direction is applied to the channel, the hole mobility will be increased; and when tensile stress along the channel direction and/or compressive stress perpendicular to the channel direction is applied to the channel, the electron mobility will be increased. Therefore, the device performance can be improved by applying stress to the channel region of the semiconductor devices.
Using silicon on insulator (SOI) substrate in replace of the silicon substrate can also achieve the effect of reducing SCE and improving device performance. The SOI technology is to introduce a buried oxygen layer between the top bulk silicon layer and the substrate the bulk silicon layer. By forming a semiconductor thin film on the insulator, the SOI material possesses the following incomparable advantages over bulk silicon: the dielectric isolation of the integrated circuit components can be realized and the parasitic latch effect in the bulk silicon CMOS circuit can be completely eliminated. The integrated circuit using the SOI material possesses advantages such as small parasitic capacitance, high integration density, fast speed, simple processability, small SCE and especially suitable for low-voltage low-power circuit. Therefore, SOI might become the mainstream technology in the deep sub-micron low-voltage, low-power integrated circuits in the future.
Meanwhile, the SOI heterostructure induces opportunities for making ultrathin silicon bulk devices. The ultrathin SOI provides an optional method for controlling the SCE by establishing a natural electrostatic barrier in the silicon dielectric interface.
In currently used technologies, a ground layer is formed under the ultrathin BOX layer in the ultrathin-SOI MOSFET to reduce the SCE and control the power consumption. However, it is very difficult to apply strong stress in the semiconductor device with this structure, and performance improvement in this device is limited.